AXI Stream basics for beginners! A Stream FIFO example in Verilog.

AXI Introduction Part 1: How AXI works and AXI-Lite transaction example

What is a FIFO in an FPGA

How the AXI-style ready/valid handshake works

10 tips for writing a clear state machine in Verilog: A UART transmitter example.

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Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)

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The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]

Zynq Part 2: Zynq Vitis Example with PL Fabric GPIO and BRAM

AXI-Stream Arbiter example

Using AXI DMA in Vivado

AXI Protocol Basics | Prepare For VLSI Industry | Join Our Advance Verification Program

What is AXI (Part 1)

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My favourite state machine, always blocks: one or many? and simplifying your SystemVerilog Style!

ZYNQ Training - session 03 - axi stream interface